Date: [June 12, 2026]
Location: Bologna, Italy
Event Link: RISC-V Summit 2026 Side Events

The RISER project is pleased to invite the European RISC-V community to participate in the workshop “Advancing RISC-V Adoption in HPC and Cloud Environments”, taking place on Friday, 12 June 2026, as part of the Side Events Programme at RISC-V Summit Europe 2026 in Bologna, Italy. and collaboration. validation, software enablement, and pathways to commercial adoption.

Program

• 09h30-09h40: Workshop introduction
• 09h40-10h30: Exploring next generation of vector architectures with hardware-software co-design in the DARE project — Teresa Cervero and Paul Carpenter, BSC [SLIDES]
• 10h30-11h00: RISC-V Accelerators: Experiences from the European PILOT Project — Carlos Puchol, BSC. [SLIDES]
• 11h00-11h15: STXMOD SoC Overview — Norbert Schuhmann, Fraunhofer IIS & ITWM. [SLIDES]
• 11h15-11h45: Coffee break
• 11h45-12h15: Integration of RISC-V Security Standards in the HIGHER Project — Nick Kossifidis, FORTH [SLIDES]
• 12h15-12h45: Composable Heterogeneous Edge Infrastructure in CAPE: From Edge AI to RISC-V Acceleration — Christian Klarhorst , Bielefeld University [SLIDES]
• 12h45-13h15: An Operating System for RISC-V based SSD Controllers — Philippe Bonnet, University of Copenhagen [SLIDES]
• 13h15-13h45: Lunch break
• 13h45-14h15: Exploiting RISC-V Vector Processors for HPC and Cloud Workloads: Experiences from the OpenCUBE Project — Ivy Peng, KTH [SLIDES]
• 14h15-14h45: Towards European RISC-V Systems: Integration Experiences from the RISER Project — Manolis Marazakis, FORTH [SLIDES]
• 14h45-15h00: Post Quantum Cryptography for RISC-V Space Systems — Leonidas Kosmidis, BSC [SLIDES]
• 14h30-15h30: Panel on “Alternative futures towards full systems based on open standards“
• 15h45-16h15: Coffee break & end of side event

Please check the official agenda link below for the exact time slot and room number for the RISER workshop.

🔗 Full Schedule & Side Events: https://riscv-europe.org/summit/2026/